Subject: Re: iSCSI v8 CRC32c

From: Luben Tuikov <[email-masked]>
Date: Tue, 27 Nov 2001 18:00:49 -0800 (PST)

Vince, 

Thanks. I'll look at it right away!

-l

--- [email-masked] wrote:
> Luben,
> 
> Your questions may have already been answered by Paul
> Koning who has
> apparently reviewed your code in detail but attached, as
> I promised, is a
> Mathematica worksheet (pdf format) that produces results
> consistent with the
> iSCSI spec. You do not need to know the syntax of
> Mathematica in order to
> follow the process, as I have inserted lots of comments.
> 
> The example I describe uses, as data, 32 decrementing
> bytes. This is one of
> hte test cases in the iSCSI document. I have added an
> undetectable error
> pattern which does not change the results obtained at the
> receiver. I think
> it would be useful to include, in the iSCSI document,
> such an undetectable
> error pattern.
> 
> I am considering writing an informative Internet Draft
> describing the
> process. I would incorporate the contents of the attached
> worksheet and also
> explain the theory behind the process. This should answer
> such questions as
> why is the expected remainder at the receiver the
> constant 1c 2d 19 ed in
> hex.  If you or others have suggestions let me know.
> 
> For those not interested in the math I summarize the
> process below.
> 
> Vicente Cavanna
> Agilent Technologies
> 
> 
> The symbols I use:
> ------------------
> 
> G is the iSCSI CRC32c polynomial.
> 
> L32 is the order-32 poly represting all 1s.
> 
> F is the poly representing 32 decrementing bytes which I
> will use as my test
> data.
> 
> ReflectedF is the poly representing F, after reversing
> the order of bits
> within each byte.
> 
> R is the remainder of the division performed at the
> transmitter.
> 
> ReflectedR is the poly obtained by reversing the order of
> bits within each
> byte of R.
> 
> FCS is the complement of ReflectedR. This is the CRC that
> you would compare
> with the iSCSI document. In the case of this example of
> 32 decrementing
> bytes the FCS is a7 e4 e4 ae in hex.
> 
> M is the transmitted message before injecting errors.
> 
> Error is the error pattern that I add to M. I use G+x^5*G
> after applying
> reflection. Any linear combination of Gs will similarly
> be undetected.
> 
> M* is the received message.
> 
> ReflectedM* is M* with the order of bits within each byte
> reversed.
> 
> Rec is the computed CRC at the receiver. You would expect
> 1c2d19ed in the
> absence of errors or if error pattern is undetectable as
> is the case in my
> example.
> 
> The process, for the case of no errors, is as follows:
> ------------------------------------------------------
> 
> At the transmitter:
> ----------------------
> 
> F is the data.
> 
> Reverse bits within each byte of F to obtain ReflectedF.
> 
> Shift ReflectedF left by 32 positions.
> 
> Add 1's to most significant 32 bits of the result
> (implemented by
> initializing CRC register to 1's).
> 
> Divide by G to obtain the 32 bit remainderR. Note that R
> is not the CRC
> shown in iSCSI document!
> 
> Reverse bits within each byte of R to obtain ReflectedR.
> 
> Add 32 1's to the result to obtain the FCS (implemented
> by complementing).
> This is what is shown in the iSCSI document and, for this
> example, is a7 e4
> e4 ae in hex.
> 
> Form the transmitted message, M, by shifting F left by 32
> positions and
> adding FCS. Note that M is derived from F rather than
> from ReflectedF even
> though the FCS is computed from ReflectedF.
> 
> M* is hte same as M since we are not introducing errors
> here. See the
> Mathematica worksheet for the case with (undetectable)
> errors.
> 
> At the receiver:
> ----------------
> 
> Receive M*
> 
> Reverse bits within each byte of M* to obtain
> ReflectedM*.
> 
> Shift the result left by 32 positions.
> 
> Add 1's to most significant 32 bits of result
> (implemented by initializing
> CRc to 1's).
> 
> Divide by G to obtain the remainder, Rec. The result (for
> the case of no
> errors) is expected to be the constant 1c 2d 19 ed in
> hex.
> 
> In the Mathcad worksheet I actually introduce an
> undetectable error pattern,
> G+G*x^5, which I reflect and add to M to obtain M*. The
> rest is the same.
> Note that the error must also be "reflected". See the
> worksheet for details.
> 
> 
>   
> 
> 
>  <<TestingCRC32cDecrBytePattern.pdf>> 
> 

> ATTACHMENT part 2 application/octet-stream
name=TestingCRC32cDecrBytePattern.pdf

=====
--

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---

From: [email-masked]
Date: Tue, 27 Nov 2001 18:39:49 -0700

Luben,

Your questions may have already been answered by Paul Koning who has
apparently reviewed your code in detail but attached, as I promised, is a
Mathematica worksheet (pdf format) that produces results consistent with the
iSCSI spec. You do not need to know the syntax of Mathematica in order to
follow the process, as I have inserted lots of comments.

The example I describe uses, as data, 32 decrementing bytes. This is one of
hte test cases in the iSCSI document. I have added an undetectable error
pattern which does not change the results obtained at the receiver. I think
it would be useful to include, in the iSCSI document, such an undetectable
error pattern.

I am considering writing an informative Internet Draft describing the
process. I would incorporate the contents of the attached worksheet and also
explain the theory behind the process. This should answer such questions as
why is the expected remainder at the receiver the constant 1c 2d 19 ed in
hex.  If you or others have suggestions let me know.

For those not interested in the math I summarize the process below.

Vicente Cavanna
Agilent Technologies

The symbols I use:
------------------

F is the poly representing 32 decrementing bytes which I will use as my test
data.

ReflectedF is the poly representing F, after reversing the order of bits
within each byte.

R is the remainder of the division performed at the transmitter.

ReflectedR is the poly obtained by reversing the order of bits within each
byte of R.

FCS is the complement of ReflectedR. This is the CRC that you would compare
with the iSCSI document. In the case of this example of 32 decrementing
bytes the FCS is a7 e4 e4 ae in hex.

Error is the error pattern that I add to M. I use G+x^5*G after applying
reflection. Any linear combination of Gs will similarly be undetected.

ReflectedM* is M* with the order of bits within each byte reversed.

Rec is the computed CRC at the receiver. You would expect 1c2d19ed in the
absence of errors or if error pattern is undetectable as is the case in my
example.

At the transmitter:
----------------------

F is the data.

Add 1's to most significant 32 bits of the result (implemented by
initializing CRC register to 1's).

Divide by G to obtain the 32 bit remainderR. Note that R is not the CRC
shown in iSCSI document!

Add 32 1's to the result to obtain the FCS (implemented by complementing).
This is what is shown in the iSCSI document and, for this example, is a7 e4
e4 ae in hex.

Form the transmitted message, M, by shifting F left by 32 positions and
adding FCS. Note that M is derived from F rather than from ReflectedF even
though the FCS is computed from ReflectedF.

M* is hte same as M since we are not introducing errors here. See the
Mathematica worksheet for the case with (undetectable) errors.

At the receiver:
----------------

Receive M*

Reverse bits within each byte of M* to obtain ReflectedM*.

Add 1's to most significant 32 bits of result (implemented by initializing
CRc to 1's).

Divide by G to obtain the remainder, Rec. The result (for the case of no
errors) is expected to be the constant 1c 2d 19 ed in hex.

In the Mathcad worksheet I actually introduce an undetectable error pattern,
G+G*x^5, which I reflect and add to M to obtain M*. The rest is the same.
Note that the error must also be "reflected". See the worksheet for details.

---

From: "Amir Shalit" <[email-masked]>
Date: Wed, 28 Nov 2001 08:31:35 -0800

Any update on adding context information (i.e. cmdSN, static target tag,
etc.)
to unsolicited data PDUs in order to facilitate simple task lookup by the
iSCSI target?

Thanks,

Amir