Subject: assumed CRC circuit performs simultaneous mult and division

From: "CAVANNA,VICENTE V (A-Roseville,ex1)" <[email-masked]>
Date: Wed, 12 Dec 2001 23:05:40 -0700

Regarding my earlier memo "effect of initializing CRC reg to 1's depends on
implementation?", here are more details and a proposed fix. This little
detail has generated a _lot_ of discussion among Luben Tuikov, Paul Koning
and myself and in fact we have not all quite agreed yet on the severity of
hte problem and how to fix it. 

Where I see the iSCSI spec deficient is in not making explicit that the
assumed circuit performs _simultaneous_ multiplication by x^32 of the
message, M(x), and division by G(x). When the spec says that the message
M(x) is multiplied by x^32 and divided by G(x), if the spec said that the
division must occur simultaneously with the multiplication by x^32, as it
does in the attached circuit, then the spec would be correct. In other
words, with that assumption the spec is correct in saying that initializing
the CRC register to 1's is equivalent (produces same remainder and quotient)
to complementing the first 32 bits of the message.

If the assumed circuit is the divide-only circuit that I also am attaching,
then initializing the CRC register to 1's, as the spec requires, will _not_
result in the correct remainder specified by iSCSI in its examples since
initializing _that_ circuit to 1's implements a different division than what
the iSCSI examples assume. 
On the other hand the receiver will still compute the same magic constant
that the iSCSi spec specifies since the magic constant is not dependent on
the actual message or its remainder but rather on the fact that there were
no errors. This is what Luben observed and what he and Paul and I have been
discussing (and still are) for a while.

This is why I am claiming that the iSCSI spec should be fixed by either:

1. making it explicit that the assumed circuit performs simultaneous
multiplication by x^32 and division by G(x) such as the attached circuit OR 

2. saying that hte most significant 32 bits of the message should be
complemented - rather than saying that the CRC register be initialized to
1s, since the effect of the last statement is implementation dependent,
whereas the effect of the first statement is independent of the
implementation.

Vince

 <<Scan_Fro.pdf>>