Subject: RE: ISCSI: found the constant for divide-only circuit!

From: "CAVANNA,VICENTE V (A-Roseville,ex1)" <[email-masked]>
Date: Fri, 14 Dec 2001 12:08:18 -0700

Added iSCSI prefix to subject line.

Actually both "example" and "preferred" seem inappropriate. How about
"reference" or "assumed" implementation? For the claims and examples in the
iSCSI spec to be correct we must refer to an implementation that performs
the following transformations (responses), after n input bits are applied,
on an initial state I(x) and an input M(x):

1. when I(x) is zero, multiplies the input, M(x), by x^32 and divides by
G(x).
2. when M(x) is zero, multiplies the initial state, I(x), by x^n and divides
by G(x).

I have previously provided a serial implementation (the simultaneous
multiply-divide circuit) that performs the above tranformations. Any
parallel implementation properly derived from such a serial implementation
should produce the same transformation and could therefore also be used as
references.

In contrast, the divide-only serial circuit that I have also provided
performs the following transformations on an initial state I(x) and an input
M(x) and iSCSI should not refer to it unless it changed some of its claims
and examples:

1. when I(x) is zero, divides the input, M(x),  by G(x)
2. when M(x) is zero, multiplies the initial state, I(x), by x^n and divides
by G(x)

Note that, by linearity of the CRC circuit, the overall response or
transformation when both I(x) and M(x) are non-zero is the sum of the
individual responses to the input and the initial state.

Vince

-----Original Message-----
From: Paul Koning [mailto:[email-masked]]
Sent: Friday, December 14, 2001 7:34 AM
To: [email-masked]
Cc: [email-masked]; [email-masked]; [email-masked];
[email-masked]; [email-masked]
Subject: RE: found the constant for divide-only circuit!

Excerpt of message (sent 13 December 2001) by CAVANNA,VICENTE V
(A-Roseville,ex1):
> I have modified the preferred implementation (simultaneous multiply-divide
> circuit) to include the control logic as Paul suggested (similar to
ethernet
> spec). By showing this circuit the iSCSI spec becomes less ambiguous and,
> just maybe, Luben and Paul will be happy men :-).

This is good.

I have one comment: I'd call this an "example" implementation rather
than "preferred".  In fact, it is quite likely not the preferred
implementation if you have to go flying along at several gigabits per
second...  And, since it's an example, I'd put it in some appendix.

There are other example implementations one might point to, for
example the 4 bits at a time table driven approach documented in the
VAX architecture manual, or the 8 bits at a time approach documented
in a paper by Stuart Wecker from sometime before 1980.  I should have
the former somewhere; the latter I don't have but I can probably come
up with a reference to it.

     paul

---

From: Paul Koning <[email-masked]>
Date: Fri, 14 Dec 2001 14:33:45 -0500 (EST)

>>>>> "Vince" == A-Roseville,ex1  <CAVANNA> writes:

 Vince> Added iSCSI prefix to subject line.  Actually both "example"
 Vince> and "preferred" seem inappropriate. How about "reference" or
 Vince> "assumed" implementation? 

That suggest you have to do it (or at least SHOULD do it) the way that
is being described, which is not the right thing to say.  The thing
that has to be stated is the mathematical statement of the CRC value,
and the rules of bit order.  That and only that is required for
interoperability.

All else is implementation detail that can certainly be helpful but is
in no way normative, and anyone is entirely free to do something
completely different so long as the PDUs come out the same.

 Vince> For the claims and examples in the
 Vince> iSCSI spec to be correct we must refer to an implementation
 Vince> that performs the following transformations (responses), after
 Vince> n input bits are applied, on an initial state I(x) and an
 Vince> input M(x):

 Vince> 1. when I(x) is zero, multiplies the input, M(x), by x^32 and
 Vince> divides by G(x).  2. when M(x) is zero, multiplies the initial
 Vince> state, I(x), by x^n and divides by G(x).

 Vince> ... In contrast, the divide-only serial circuit that I have also
 Vince> provided performs the following transformations on an initial
 Vince> state I(x) and an input M(x) and iSCSI should not refer to it
 Vince> unless it changed some of its claims and examples:

 Vince> 1. when I(x) is zero, divides the input, M(x), by G(x) 2. when
 Vince> M(x) is zero, multiplies the initial state, I(x), by x^n and
 Vince> divides by G(x)

Those are four example implementations, I think.  I'm not sure if
giving four examples is better than giving just one, or more
confusing.  (Perhaps the right answer is to give no examples, as Pat
suggested, retaining only the formal mathematical definition; that
would match the practice of all other datacomm specs other than
Ethernet that I know of.)

      paul