Subject: RE: ISCSI: found the constant for divide-only circuit!

From: "CAVANNA,VICENTE V (A-Roseville,ex1)" <[email-masked]>
Date: Fri, 14 Dec 2001 13:23:50 -0700

I have to agree that a mathematical description is the best. I had it all
worked out months ago until I realized about the bit reversal within each
byte which broke my math. At that time I argued against the bit reversal and
lost - including my interest. Luben and you rekindled my interest.  Luben
and I have now pretty much developed the necessary math to unambiguously
show the steps but we still have some disagreements on how to present it. In
the process we discovered the need to specify the reference circuit.

In the meantime I was trying to get the iSCSI spec fixed because, as it
stands, it makes an implicit assumption about the implementation without
which its claims are wrong. Either the claims must be fixed or the assumed
circuit must be specified. 

One way to specify the circuit is to show the reference implementation and
to say that any circuit that performs the same function, ie. has the exact
same response to initial state and to the input is also acceptable.

Another way is to describe the response of the implied circuit after the
application of n input bits is:

1. when I(x) is zero, multiplies the input, M(x), by x^32 and divides by
G(x).
2. when M(x) is zero, multiplies the initial state, I(x), by x^n and divides
by G(x).

where I(x) represents the initial state of the CRC register and M(x)
represents the input.

Vince

|-----Original Message-----
|From: Paul Koning [mailto:[email-masked]]
|Sent: Friday, December 14, 2001 11:34 AM
|To: [email-masked]
|Cc: [email-masked]
|Subject: RE: ISCSI: found the constant for divide-only circuit!
|
|
|>>>>> "Vince" == A-Roseville,ex1  <CAVANNA> writes:
|
| Vince> Added iSCSI prefix to subject line.  Actually both "example"
| Vince> and "preferred" seem inappropriate. How about "reference" or
| Vince> "assumed" implementation? 
|
|That suggest you have to do it (or at least SHOULD do it) the way that
|is being described, which is not the right thing to say.  The thing
|that has to be stated is the mathematical statement of the CRC value,
|and the rules of bit order.  That and only that is required for
|interoperability.
|
|All else is implementation detail that can certainly be helpful but is
|in no way normative, and anyone is entirely free to do something
|completely different so long as the PDUs come out the same.
|
| Vince> For the claims and examples in the
| Vince> iSCSI spec to be correct we must refer to an implementation
| Vince> that performs the following transformations (responses), after
| Vince> n input bits are applied, on an initial state I(x) and an
| Vince> input M(x):
|
| Vince> 1. when I(x) is zero, multiplies the input, M(x), by x^32 and
| Vince> divides by G(x).  2. when M(x) is zero, multiplies the initial
| Vince> state, I(x), by x^n and divides by G(x).
|
| Vince> ... In contrast, the divide-only serial circuit that I 
|have also
| Vince> provided performs the following transformations on an initial
| Vince> state I(x) and an input M(x) and iSCSI should not refer to it
| Vince> unless it changed some of its claims and examples:
|
| Vince> 1. when I(x) is zero, divides the input, M(x), by G(x) 2. when
| Vince> M(x) is zero, multiplies the initial state, I(x), by x^n and
| Vince> divides by G(x)
|
|Those are four example implementations, I think.  I'm not sure if
|giving four examples is better than giving just one, or more
|confusing.  (Perhaps the right answer is to give no examples, as Pat
|suggested, retaining only the formal mathematical definition; that
|would match the practice of all other datacomm specs other than
|Ethernet that I know of.)
|
|      paul
|